New chip tests cooling solutions for stacked microelectronics

As demand grows for more powerful and efficient microelectronics systems, industry is turning to 3D integration — stacking chips on top of each other. This vertically layered architecture could allow high-performance processors, like those used for artificial intelligence, to be packaged closely with other highly specialized chips for communication or imaging. But technologists everywhere face a major challenge: how to prevent these stacks from overheating.Now, MIT Lincoln Laboratory has developed a specialized chip to test and validate cooling solutions for packaged chip stacks. The chip dissipates extremely high power, mimicking high-performance logic chips, to generate heat through the silicon layer and in localized hot spots. Then, as cooling technologies are applied to the packaged stack, the chip measures temperature changes. When sandwiched in a stack, the chip will allow researchers to study how heat moves through stack layers and benchmark progress in keeping them cool. “If you have just a single chip, you can cool it from above or below. But if you start stacking several chips on top of each other, the heat has nowhere to escape. No cooling methods exist today that allow industry to stack multiples of these really high-performance chips,” says Chenson Chen, who led the development of the chip with Ryan Keech, both of the laboratory’s Advanced Materials and Microsystems Group.The benchmarking chip is now being used at HRL Laboratories, a research and development company co-owned by Boeing and General Motors, as they develop cooling systems for 3D heterogenous integrated (3DHI) systems. Heterogenous integration refers to the stacking of silicon chips with non-silicon chips, such as III-V semiconductors used in radio-frequency (RF) systems.   “RF components can get very hot and run at very high powers — it adds an extra layer of complexity to 3D integration, which is why having this testing capability is so needed,” Keech says.The Defense Advanced Research Projects Agency (DARPA) funded the laboratory’s development of the benchmarking chip to support the HRL program. All of this research stems from DARPA’s Miniature Integrated Thermal Management Systems for 3D Heterogeneous Integration (Minitherms3D) program.For the Department of Defense, 3DHI opens new opportunities for critical systems. For example, 3DHI could increase the range of radar and communication systems, enable the integration of advanced sensors on small platforms such as uncrewed aerial vehicles, or allow artificial intelligence data to be processed directly in fielded systems instead of remote data centers.The test chip was developed through collaboration between circuit designers, electrical testing experts, and technicians in the laboratory’s Microelectronics Laboratory. The chip serves two functions: generating heat and sensing temperature. To generate heat, the team designed circuits that could operate at very high power densities, in the kilowatts-per-square-centimeter range, comparable to the projected power demands of high-performance chips today and into the future. They also replicated the layout of circuits in those chips, allowing the test chip to serve as a realistic stand-in. “We adapted our existing silicon technology to essentially design chip-scale heaters,” says Chen, who brings years of complex integration and chip design experience to the program. In the 2000s, he helped the laboratory pioneer the fabrication of two- and three-tier integrated circuits, leading early development of 3D integration.The chip’s heaters emulate both the background levels of heat within a stack and localized hot spots. Hot spots often occur in the most buried and inaccessible areas of a chip stack, making it difficult for 3D-chip developers to assess whether cooling schemes, such as microchannels delivering cold liquid, are reaching those spots and are effective enough.That’s where temperature-sensing elements come in. The chip is distributed with what Chen likens to “tiny thermometers” that read out the temperature in multiple locations across the chip as coolants are applied.These thermometers are actually diodes, or switches that allow current to flow through a circuit as voltage is applied. As the diodes heat up, the current-to-voltage ratio changes. “We’re able to check a diode’s performance and know that it’s 200 degrees C, or 100 degrees C, or 50 degrees C, for example,” Keech says. “We thought creatively about how devices could fail from overheating, and then used those same properties to design useful measurement tools.”Chen and Keech — along with other design, fabrication, and electrical test experts across the laboratory — are now collaborating with HRL Laboratories researchers as they couple the chip with novel cooling technologies, and integrate those technologies into a 3DHI stack that could boost RF signal power. “We need to cool the heat equivalent of more than 190 laptop CPUs [central processing units], but in the size of a single CPU package,” Christopher Roper, co-principal investigator at HRL, said in a recent press release announcing their program.According to Keech, the rapid timeline for delivering the chip was a challenge overcome by teamwork through all phases of the chip’s design, fabrication, test, and 3D heterogenous integration.”Stacked architectures are considered the next frontier for microelectronics,” he says. “We want to help the U.S. government get ahead in finding ways to integrate them effectively and enable the highest performance possible for these chips.”The laboratory team presented this work at the annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech), held March 17-20.