TAIPEI, Sept. 2, 2026 /PRNewswire/ — The global race to build artificial intelligence infrastructure is entering a new phase. For the past several years, much of the competition has centered on securing the most powerful AI accelerators. But as hyperscalers pour billions of dollars into data centers while developing more of their own silicon, another strategic question is moving to the forefront: how to efficiently connect an increasingly diverse mix of AI chips and turn them into computing systems that can operate at massive scale.
The scale of investment makes that question increasingly important. McKinsey estimates that nearly $7 trillion in global data center capital expenditure could be required by 2030, including about $5.2 trillion for facilities supporting AI workloads. Under its continued-momentum scenario, AI-related data center capacity demand could rise to approximately 156 gigawatts by 2030, roughly 3.5 times its 2025 level. As spending expands across accelerators, networking, storage, power and cooling, the architecture connecting these systems is becoming a larger part of the infrastructure equation.
At the same time, the AI silicon landscape itself is becoming more diverse. Hyperscalers are increasingly combining general-purpose GPUs with custom accelerators optimized for their own workloads. Google, Amazon, Microsoft and Meta have all pursued proprietary AI silicon strategies, while partnerships between cloud companies and semiconductor suppliers continue to deepen. The trend was underscored again in August, when Google expanded its custom AI chip partnership with Marvell — another sign that hyperscalers are seeking greater control and diversification across their AI hardware stacks.
Against this backdrop, a new DIGITIMES Intelligence report finds that AI infrastructure is moving toward a multi-architecture environment, where no single chip platform or interconnect standard is likely to serve every workload. As cloud service providers deploy their own AI ASICs alongside GPUs, competition is intensifying around AI fabric — the interconnect systems that allow accelerators, nodes, racks and clusters to operate together as a unified computing infrastructure.
The report identifies two critical layers of this competition. Scale-up handles high-speed, low-latency connections among accelerators within a node or rack, while scale-out connects nodes, racks and clusters across a larger computing environment. As new AI chip architectures proliferate, each introduces different requirements for bandwidth, latency, power efficiency and interoperability — making the coordination between these two layers increasingly important.
The broader industry is already responding to this challenge. Open interconnect initiatives such as UALink are gaining momentum as AI infrastructure providers seek greater interoperability and flexibility across accelerator platforms. The UALink Consortium argues that increasingly complex training clusters and inference workloads are placing new demands on every layer of the fabric, while proprietary interconnect approaches can limit procurement flexibility and ecosystem choice.
DIGITIMES Intelligence finds that the physical technologies supporting these two layers are also diverging. Scale-up continues to rely heavily on copper and board-level electrical signaling for short-reach, ultra-low-latency connections. Scale-out, however, is moving increasingly toward optical interconnects as distance, bandwidth and power requirements rise between nodes and racks.
That shift is creating a broader competitive landscape across the semiconductor and networking supply chain. DIGITIMES Intelligence identifies three major layers: platform chip vendors controlling switch architectures and fabric specifications; active interconnect IC suppliers providing signal conditioning and electro-optical conversion; and physical interconnect vendors supplying the cables, connectors and optical components required to deploy those architectures at scale.
Those boundaries, however, are beginning to blur. The report finds that several interconnect IC suppliers are expanding beyond their traditional specialties into adjacent layers of the technology stack. As AI architectures diversify, vendors increasingly have an incentive to control more of the fabric — because the performance and economic cost of getting interconnect design wrong rises sharply as systems scale.
The implications extend beyond networking. As AI infrastructure becomes more heterogeneous, competitive advantage may increasingly depend not only on who builds the fastest accelerator, but on who can integrate different compute architectures most efficiently. That shift could influence semiconductor design, cloud infrastructure strategy, networking standards and capital allocation across the data center ecosystem. For Taiwan, the transition is particularly relevant because the opportunity extends beyond advanced chips into the broader hardware ecosystem — including switches, cables, connectors, optical components and system manufacturing.
The new DIGITIMES Intelligence report examines how the rise of custom AI silicon is reshaping scale-up and scale-out architectures, the competitive dynamics across AI fabric, and the semiconductor, networking and physical interconnect suppliers positioned to benefit as multi-architecture AI infrastructure expands.
For more information: DIGITIMES Intelligence – AI Fabric Competition Report
https://dgt.ms/reportAI_fabriccompetition_prnewswire
About DIGITIMES
DIGITIMES is a Decision Intelligence platform rooted at the core of the industry, dedicated to helping global decision-makers navigate change and formulate strategies through first-hand insights and AI–driven analysis. We integrate intelligence services, forward-looking research, and influence marketing to provide comprehensive support from insights to execution—continuously defining the future with clarity and serving as a long–term strategic partner for businesses moving forward.
